SH7713 Datasheet, PDF (667/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
No.
Time Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set RXE bit in SICTR register to 1
Store receive data from RXD_SIO
3 _{in SIRDR synchronously with SIOFSYNC}
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and the upper limit value of FIFO
request
Set to enable reception
Enable reception when the
frame synchronous signal is
input
Submit reception request
according to the limit
value of receive FIFO
4
RDREQ=1? ^No
Yes
Reception
5
Read SIRDR
Read receive data
Transfer
No
ended?
6
Yes
Clear RXE bit in SICTR to 0
End
Set to disable reception
End reception
Figure 17.12 Example of Reception Operation in Slave Mode
Transmission/Reception Reset: The SIOF can separately reset the transmission and reception
units by setting the following bits to 1.
• Transmission reset: TXRST bit in SICTR
• Reception reset: RXRST bit in SICTR
Rev.1.50 Aug. 30, 2006 Page 627 of 860
REJ09B0288-0150