SH7713 Datasheet, PDF (333/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
6. Note the following when a break occurs in a delay slot.
If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break
does not occur until the branch destination of the RTE instruction.
7. User breaks are disabled during UBC module standby mode. Do not read from or write to the
UBC registers during UBC module standby mode; the values are not guaranteed.
8. When the repeat loop of the DSP extended function is used, even though a break condition is
satisfied during execution of the entire repeat loop or several instructions in the repeat loop, the
break may be held. For details, see section 4, Exception Handling.
Rev.1.50 Aug. 30, 2006 Page 293 of 860
REJ09B0288-0150