SH7713 Datasheet, PDF (373/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
BACK
BREQ
Bus
mastership
controller
CMNCR
Internal master
module
Internal slave
module
WAIT
Wait
controller
CS0WCR
CS6BWCR
CS0, CS2, CS3,
CS4, CS5A, CS5B,
CS6A, CS6B
MD5 to MD3
A25 to A0,
D31 to D0
BS, RD/WR, RD,
WE3(BE3) to WE0(BE0),
RAS, CAS,
CKE, DQMxx,
CE2A, CE2B
Area
controller
Memory
controller
CS0BCR
CS6BBCR
IOIS16
REFOUT
Interrupt
controller
Refresh
controller
SDCR
RTCSR
RTCNT
Comparator
RTCOR
BSC
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
CSnBCR: CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
Figure 12.1 Block Diagram of BSC
Rev.1.50 Aug. 30, 2006 Page 333 of 860
REJ09B0288-0150