SH7713 Datasheet, PDF (38/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Table 12.13
Table 12.13
Table 12.14
Table 12.15
Table 12.15
Table 12.16
Table 12.16
Table 12.17
Table 12.17
Table 12.18
Table 12.19
Table 12.20
Table 12.21
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (2)-1........................................................................ 405
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (2)-2........................................................................ 406
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (3)........................................................................... 408
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (4)-1........................................................................ 409
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (4)-2........................................................................ 410
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (5)-1........................................................................ 411
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (5)-2........................................................................ 412
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (6)-1........................................................................ 413
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (6)-2........................................................................ 414
Relationship between Access Size and Number of Bursts................................ 415
Access Address in SDRAM Mode Register Write ........................................... 435
Output Addresses when EMRS Command is Issued ........................................ 438
Relationship between Bus Width, Access Size, and Number of Bursts............ 441
Section 13 Direct Memory Access Controller (DMAC)
Table 13.1 Pin Configuration.................................................................................................. 461
Table 13.2 DMARS Setting.................................................................................................... 474
Table 13.3 Selecting External Request Modes with RS Bits .................................................. 477
Table 13.4 Selecting External Request Detection with DL, DS Bits ...................................... 478
Table 13.5 Selecting External Request Detection with DO Bit .............................................. 478
Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits ..... 479
Table 13.7 Supported DMA Transfers.................................................................................... 482
Table 13.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 488
Section 14 Timer Unit (TMU)
Table 14.1 TMU Interrupt Sources......................................................................................... 504
Section 15 Realtime Clock (RTC)
Table 15.1 Pin Configuration.................................................................................................. 507
Table 15.2 Recommended Oscillator Circuit Constants (Recommended Values).................. 528
Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.1 Pin Configuration.................................................................................................. 534
Rev.1.50 Aug. 30, 2006 Page xxxviii of xl