SH7713 Datasheet, PDF (43/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
Cache memory:
• 32-kbyte cache, mixture of instructions and data
• 512-entry, 4-way set associative, 16-byte block length
• Write-back, write-through, LRU replacement algorithm
• 1-stage write-back buffer
X/Y memory:
• Three independent read/write ports
8-/16-/32-bit access from the CPU
Maximum two 16-bit accesses from the DSP
8-/16-/32-bit access from the DMAC
32-bit access from the E-DMAC
• A total of 16 kbytes memory (8-kbyte RAM each for X- and Y-memory)
Interrupt controller (INTC):
• Supports seven external interrupt pins (NMI, IRQ5 to IRQ0)
• Supports fifteen level interrupt pins (IRL3 to IRL0)
• Supports one interrupt request output pin (IRQOUT)
• On-chip peripheral interrupt: Priority level is independently selected for each module
• Supports software vector mode
• Selection of falling/rising/high/low
User break controller (UBC):
• Address, data value, access type, and data size are available for setting as break conditions
• Supports the sequential break function
• Two break channels
On-Chip Oscillation Circuits:
• Clock source selectable between an external supply (EXTAL or CKIO) and crystal resonator
The internal clock and peripheral clock can be adjusted by setting the PLL circuit and division
ratio.
• Three types of clocks generated:
CPU clock (I clock): 200 MHz (max)
Bus clock (B clock): 66 MHz (max)
Rev.1.50 Aug. 30, 2006 Page 3 of 860
REJ09B0288-0150