SH7713 Datasheet, PDF (572/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
• Choice of serial clock source: Internal clock from the baud rate generator or external clock
from the SCIF0CK and SCIF1CK pins.
• There are four interrupt sourcestransmit-FIFO-data-empty, receive-FIFO-data-full, receive-
error, and break. Each source can be requested independently.
• The DMA controller (DMAC) can be activated to execute a data transfer in the event of a
transmit-FIFO-data-empty or receive-FIFO-data-full.
• On-chip modem control functions (CTS0/CTS1 and RTS0/RTS1)
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
consumption.
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
the receive data in the receive FIFO register, can be ascertained.
• On reception a time out error (DR) can be detected
• The contents of the transmit FIFO data register (SCFTDR) and receive FIFO data register
(SCFRDR) are undefined after a power-on or manual reset. Other registers are initialized by a
power-on or manual reset, and retain their values in standby mode and in the module standby
state.
Rev.1.50 Aug. 30, 2006 Page 532 of 860
REJ09B0288-0150