SH7713 Datasheet, PDF (134/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
CPU
XAB
[15:0]
X memory
Y memory
YAB
[15:0]
DSP unit
XDB
[15:0]
YDB
[15:0]
CDB
[31:0]
LAB
[31:0]
LDB
[31:0]
DSR
A0G
A0
A1G
A1
M0
M1
X0
X1
Y0
Y1
[Legend]
XAB: X bus (address)
XDB: X bus (data)
YAB: Y bus (address)
YDB: Y bus (data)
LAB: L bus (address)
LDB: L bus (data)
CDB: C bus (data)
Figure 3.4 DSP Registers and Bus Connections
Double Data Transfer Instructions (MOVX.W, MOVY.W, MOVX.L, MOVY.L): With
double data transfer group instructions, X memory and Y memory can be accessed in parallel.
In this case, the specific buses called X bus and Y bus are used to access X memory and Y
memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict
occurs among X, Y, and L buses.
Load instructions for X memory specify the X0 or X1 register as the destination operand. Load
instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers
for X or Y memory specify the A0 or A1 register as the source operand. These instructions use
only word data (16 bits). When a word data transfer instruction is executed, the upper word of
register operand is used. To load word data, data is loaded to the upper word of the destination
register and the lower word of the destination register is automatically cleared to 0.
Rev.1.50 Aug. 30, 2006 Page 94 of 860
REJ09B0288-0150