SH7713 Datasheet, PDF (751/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Reception flowchart
This LSI + memory
E-DMAC
Receive FIFO
EtherC
Ethernet
EtherC/E-DMAC
initialization
Receive
descriptor and
receive buffer
setting
Start of reception
Receive descriptor read
Frame reception
Receive data transfer
Receive descriptor
write-back
Receive descriptor
read
Receive data transfer
Receive descriptor
write-back
Receive descriptor read
(preparation for receiving
the next frame)
Reception
completed
[Legend]
EtherC/E-DMAC initialization: Executes a software reset with the SWR bit in EDMR set to 1.
Receive descriptor and receive buffer setting: Sets receive descriptors and receive buffers, and sets EtherC and E-DMAC
registers, then writes 1 to the RE bit in ECMR and the RR bit in EDRRR.
Start of reception: Occurs when 1 is written to the RE bit in ECMR and the RR bit in EDRRR.
Receive descriptor read: The E-DMAC reads a receive descriptor.
Receive data transfer: Writes receive data from the receive FIFO to the receive buffer by using DMA transfer by the E-DMAC.
Receive descriptor write-back: The E-DMAC writes 0 to the RACT bit and writes the receive status to the receive descriptor.
Figure 19.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor)
Rev.1.50 Aug. 30, 2006 Page 711 of 860
REJ09B0288-0150