SH7713 Datasheet, PDF (678/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.2 Input/Output Pins
Table 18.1 lists the pin configuration of the EtherC.
Table 18.1 Pin Configuration
Name
Abbreviation I/O Function
Transmit clock
TX-CLK0*¹ I
TX-EN, ETXD3 to ETXD0, TX-ER timing reference
signal
Receive clock
RX-CLK0*¹ I
RX-DV, ERXD3 to ERXD0, RX-ER timing reference
signal
Transmit enable TX-EN0*¹ O
Indicates that transmit data is ready on ETXD3 to
ETXD0
Transmit data
ETXD03 to O
ETXD00*¹
4-bit transmit data
Transmit error
TX-ER0*¹
O
Notifies PHY_LSI of error during transmission
Receive data valid RX-DV0*¹ I
Indicates that valid receive data is on ERXD3 to
ERXD0
Receive data
ERXD03 to I
ERXD00*¹
4-bit receive data
Receive error
RX-ER0*¹ I
Identifies error state occurred during data reception
Carrier detection CRS0*¹
I
Carrier detection signal
Collision detection COL0*¹
I
Collision detection signal
Management data MDC0*¹
clock
O
Reference clock signal for information transfer via
MDIO
Management data MDIO0*¹
I/O
I/O Bidirectional signal for exchange of management
information between this LSI and PHY
Link status
LNKSTA0 I
Inputs link status from PHY
General-purpose EXOUT0
O
Signal indicating value of register-bit (ECMR.ELB)
external output
Wake-On-LAN
WOL0
O Signal indicating reception of Magic Packet
Bus release request ARBUSY*² O
Signal indicating bus release request when the
threshold value set for the data volume in the receive
FIFO has been exceeded
Notes: 1. MII signal conforming to IEEE802.3u
2. Refer to section 19, Ethernet Controller Direct Memory Access Controller (E-DMAC)
and section 19.2.18, Overflow Alert FIFO Threshold Register (FCFTR), and section
19.3.5, Receive FIFO Overflow Alert Signal (ARBUSY).
Rev.1.50 Aug. 30, 2006 Page 638 of 860
REJ09B0288-0150