SH7713 Datasheet, PDF (170/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
The DC bit is set when the operation result is a negative value, and cleared when the operation
result is zero or a positive value.
3. Zero Value Mode: CS[2:0] = 010
The DC bit is set when the operation result is zero; otherwise it is cleared.
4. Overflow Mode: CS[2:0] = 011
The DC bit is set when an overflow occurs.
5. Signed Greater Than Mode: CS[2:0] = 100
The DC bit is always cleared.
6. Signed Greater Than or Equal Mode: CS[2:0] = 101
The DC bit is always cleared.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
• Overflow Protection
The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section
3.5.11, Overflow Protection, for details.
Rev.1.50 Aug. 30, 2006 Page 130 of 860
REJ09B0288-0150