SH7713 Datasheet, PDF (95/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction
Instruction Code Operation
Execution
Privilege States T Bit
Indicated by mnemonic.
Indicated in MSB ↔
LSB order.
Explanation of Symbols Explanation of Symbols
OP.Sz SRC, DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
.........
1111: R15
Rn: Destination register iiii: Immediate data
imm: Immediate data
dddd: Displacement^*2
disp: Displacement
Indicates summary of
operation.
Indicates a
privileged
instruction.
Explanation of Symbols
→, ←: Transfer direction
(xx): Memory operand
M/Q/T: Flag bits in SR
&: Logical AND of each bit
|: Logical OR of each bit
^: Exclusive logical OR of
each bit
~: Logical NOT of each bit
Value
Value of T
when no bit after
wait states instruction
are
is
inserted^*1 executed
Explanatio
n of
Symbols
—: No
change
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is also used
by the following instruction
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
Rev.1.50 Aug. 30, 2006 Page 55 of 860
REJ09B0288-0150