SH7713 Datasheet, PDF(280/904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7713 Datasheet, PDF (280/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

◁

Section 8 Interrupt Controller (INTC)

The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral

module interrupt handling.

8.3.5 Interrupt Exception Handling and Priority

There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The

priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and

level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt

request is ignored.

Tables 8.2 and 8.3 list the codes for the interrupt event registers (INTEVT and INTEVT2) and the

order of interrupt priority.

Each interrupt source is assigned a unique code by INTEVT or INTEVT2. The start address of the

interrupt service routine is common for each interrupt source. This is why, for instance, the value

of INTEVT or INTEVT2 is used as an offset at the start of the interrupt service routine and

branched to in order to identify the interrupt source.

IRQ interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15

for each module by setting interrupt priority registers A to I (IPRA to IPRI). A reset assigns

priority level 0 to IRQ and on-chip peripheral module interrupts.

If the same priority level is assigned to two or more interrupt sources and interrupts from those

sources occur simultaneously, their priority order is the default priority order indicated at the right

in tables 8.2 and 8.3.

Table 8.2 Interrupt Exception Handling Sources and Priority (IRQ Mode)

Interrupt Source

NMI

H-UDI

IRQ

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

Interrupt

Priority

Priority

IPR

within IPR Default

Interrupt Code*1 (Initial Value) (Bit Numbers) Setting Unit Priority

Hâ²1C0*2

16

ï£§

ï£§

High

Hâ²5E0*2

15

ï£§

ï£§

Hâ²600*3

0 to 15 (0) IPRC (3 to 0) ï£§

Hâ²620*3

0 to 15 (0) IPRC (7 to 4) ï£§

Hâ²640*3

0 to 15 (0) IPRC (11 to 8) ï£§

Hâ²660*3

0 to 15 (0) IPRC (15 to 12) ï£§

Hâ²680*3

0 to 15 (0) IPRD (3 to 0) ï£§

Hâ²6A0*3

0 to 15 (0) IPRD (7 to 4) ï£§

Low

Rev.1.50 Aug. 30, 2006 Page 240 of 860

REJ09B0288-0150

▷