SH7713 Datasheet, PDF (722/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value
20
TDEIP
0
19
TFUFIP
0
18
FRIP
0
17
RDEIP
0
16
RFOFIP 0
15 to 12 
All 0
11
CNDIP
0
10
DLCIP
0
9
CDIP
0
8
TROIP
0
R/W Description
R/W Transmit Descriptor Empty Interrupt Enable
0: Transmit descriptor empty interrupt is disabled
1: Transmit descriptor empty interrupt is enabled
R/W Transmit FIFO Underflow Interrupt Enable
0: Underflow interrupt is disabled
1: Underflow interrupt is enabled
R/W Frame Received Interrupt Enable
0: Frame received interrupt is disabled
1: Frame received interrupt is enabled
R/W Receive Descriptor Empty Interrupt Enable
0: Receive descriptor empty interrupt is disabled
1: Receive descriptor empty interrupt is enabled
R/W Receive FIFO Overflow Interrupt Enable
0: Receive FIFO overflow interrupt is disabled
1: Receive FIFO overflow interrupt is enabled
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Carrier Not Detect Interrupt Enable
0: Carrier not detect interrupt is disabled
1: Carrier not detect interrupt is enabled
R/W Detect Loss of Carrier Interrupt Enable
0: Detect loss of carrier interrupt is disabled
1: Detect loss of carrier interrupt is enabled
R/W Delayed Collision Detect Interrupt Enable
0: Delayed collision detect interrupt is disabled
1: Delayed collision detect interrupt is enabled
R/W Transmit Retry Over Interrupt Enable
0: Transmit retry over interrupt is disabled
1: Transmit retry over interrupt is enabled
Rev.1.50 Aug. 30, 2006 Page 682 of 860
REJ09B0288-0150