SH7713 Datasheet, PDF (497/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal
buses: a cache bus, internal bus, and peripheral bus. The CPU and cache memory are connected to
the cache bus. Internal bus masters other than the CPU and bus state controller are connected to
the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal
memories other than the cache memory and debugging modules such as a UBC and AUD are
connected bidirectionally to the cache bus and internal bus. Access from the cache bus to the
internal bus is enabled but access from the internal bus to the cache bus is disabled. This gives rise
to the following problems.
Internal bus masters such as DMAC or E-DMAC other than the CPU can access on-chip memory
other than the cache memory but cannot access the cache memory. If an on-chip bus master other
than the CPU writes data to an external memory other than the cache, the contents of the external
memory may differ from that of the cache memory. To prevent this problem, if the external
memory whose contents is cached is written by an on-chip bus master other than the CPU, the
corresponding cache memory should be purged by software.
If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the
CPU latches the data and completes the read access. If the cache does not store data, the CPU
performs four contiguous longword read cycles to perform cache fill operations via the internal
bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary
(4n + 2), the CPU performs four contiguous longword accesses to perform a cache fill operation
on the external interface. For a non-Cacheable area, the CPU performs access according to the
actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs
longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs
word access.
For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first
accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus.
In a write cycle for the cache area, the write cycle operation differs according to the cache write
methods.
In write-back mode, the cache is first searched. If data is detected at the address corresponding to
the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written
until data in the corresponding address is re-written. If data is not detected at the address
corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to
the internal buffer, 16-byte data including the data corresponding to the address is then read, and
data in the corresponding access of the cache is finally modified. Following these operations, a
write-back cycle for the saved 16-byte data is executed.
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