SH7713 Datasheet, PDF (711/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
• Overflow alert FIFO threshold register (FCFTR)
• Transmit interrupt register (TRIMD)
19.2.1 E-DMAC Mode Register (EDMR)
EDMR is a 32-bit readable/writable register that specifies E-DMAC resetting and transmit/receive
descriptor length. This register is to be set before the TR bit in EDTRR or the RR bit in EDRRR is
set to 1. If a software reset is executed with this register during data transmission, abnormal data
may be transmitted on the line. Execute a software reset with this register before specifying
transmit/receive descriptor length and modifying the settings of TDLAR, RDLAR, and so forth,
the setting of ECMR (EtherC mode register), and the settings of registers related to E-DMAC and
EtherC operation. The time required for completion of EtherC and E-DMAC initialization from a
software reset with this register is 64 cycles of the internal bus clock Bφ. Therefore, registers of
the EtherC and E-DMAC should be accessed after 64 cycles of the internal bus clock Bφ has
elapsed.
Initial
Bit
Bit Name Value R/W Description
31 to 6 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
5
DL1
0
R/W Descriptor Length
4
DL0
0
R/W These bits specify the descriptor length. (See section
19.3.1, Descriptors and Descriptor List.)
00: 16 bytes
01: 32 bytes
10: 64 bytes
11: Reserved (setting prohibited)
3 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.50 Aug. 30, 2006 Page 671 of 860
REJ09B0288-0150