SH7713 Datasheet, PDF (316/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
Initial
Bit
Bit Name Value R/W Description
11
PCTE
0
R/W PC Trace Enable
0: Disables PC trace
1: Enables PC trace
10
PCBA
0
R/W PC Break Select A
Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
execution
1: PC break of channel A is set after instruction
execution
9

0
R
Reserved
8

0
R
These bits are always read as 0. The write value should
always be 0.
7
DBEB
0
R/W Data Break Enable B
Selects whether or not the data bus condition is
included in the break condition of channel B.
0: No data bus condition is included in the condition of
channel B
1: The data bus condition is included in the condition of
channel B
6
PCBB
0
R/W PC Break Select B
Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
execution
1: PC break of channel B is set after instruction
execution
5

0
R
Reserved
4

0
R
These bits are always read as 0. The write value should
always be 0.
Rev.1.50 Aug. 30, 2006 Page 276 of 860
REJ09B0288-0150