SH7713 Datasheet, PDF (299/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name
5
TXI1R
4
ERI1R
3 to 0 
Initial Value R/W
0
R
0
R
All 0
R
Description
TXI1 Interrupt Request
Indicates whether the TXI1 (SIOF1) interrupt
request is generated.
0: TXI1 interrupt request is not generated
1: TXI1 interrupt request is generated
ERI1 Interrupt Request
Indicates whether the ERI1 (SIOF1) interrupt
request is generated.
0: ERI1 interrupt request is not generated
1: ERI1 interrupt request is generated
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.50 Aug. 30, 2006 Page 259 of 860
REJ09B0288-0150