SH7713 Datasheet, PDF (733/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
31 to 19 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
18
RFF2
1
17
RFF1
1
16
RFF0
1
R/W Receive FIFO Overflow Alert Signal Output Threshold
R/W _{000: When one receive frame has been stored in the}
R/W
receive FIFO
001: When two receive frames have been stored in
the receive FIFO
:
:
110: When seven receive frames have been stored in
the receive FIFO
111: When eight receive frames have been stored in
the receive FIFO
15 to 3 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
RFD2
1
R/W Receive FIFO Overflow Alert Signal Output Threshold
1
RFD1
1
R/W 000: When (256 − 32) bytes of data is stored in the
0
RFD0
1
R/W
receive FIFO
001: When (512 − 32) bytes of data is stored in the
receive FIFO
:
:
110: When (1792 − 32) bytes of data is stored in the
receive FIFO
111: When (2048 − 64) bytes of data is stored in the
receive FIFO
Rev.1.50 Aug. 30, 2006 Page 693 of 860
REJ09B0288-0150