SH7713 Datasheet, PDF (42/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
• Space identifier ASID: 8 bits, 256 logical address spaces
• Supports five-stage pipeline
DSP:
• Mixture of 16-bit and 32-bit instructions
• 32-/40-bit internal data bus
• Multiplier, ALU, and barrel shifter
• 16-bit × 16-bit → 32-bit one cycle multiplier
• Large-capacity DSP data registers
Six 32-bit data registers
Two 40-bit data registers
• Supports extended harvard architecture for DSP data bus
Two data buses
One instruction bus
• Maximum four parallel operations
ALU, multiply, and two load/store
• Two addressing units to generate addresses for two memory access
• Supports DSP data addressing modes
Increment and indexing (with or without modulo addressing)
• Zero-overhead repeat loop control
• Conditional execution instructions
• Supports user DSP mode and privileged DSP mode
Memory management unit (MMU):
• 4 Gbytes of address space, 256 address spaces (8-bit ASID)
• Page unit sharing
• Supports multiple page sizes
1 kbyte or 4 kbytes
• Supports 128-entry, 4-way set associative TLB
• Supports software selection of replacement way and random-replacement algorithms
• Contents of TLB are directly accessible by address mapping
Rev.1.50 Aug. 30, 2006 Page 2 of 860
REJ09B0288-0150