SH7713 Datasheet, PDF (871/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
24.3.9 SCIF Module Signal Timing
Table 24.11 SCIF Module Signal Timing
Module
(Conditions: V_CCQ = V_CCQ-RTC = 3.0 to 3.6 V, V_CC = V_CC-PLL1 = V_CC-PLL2 = 1.4 to 1.6 V,
V Q = V = V Q-RTC = V -PLL1 = V -PLL2 = 0 V, T = –20 to 75°C)
SS
SS
SS
SS
SS
a
Item
Symbol Min. Max.
Unit Figure
SCIF0,
SCIF1
Input clock
cycle
Clock
t_Scyc
synchronization
12
—
t_Pcyc
24.51
24.52
Asynchroniza-
tion
4
—
Input clock rise time
t
SCKR
Input clock fall time
t
SCKF
Input clock pulse width
t_SCKW
Transmission data delay time t
TXD
Receive data setup time
t_RXS
(clock synchronization)
—
1.5
—
1.5
0.4
0.6
t_Scyc
—
3 t_Pcyc* + 50 ns
2 t_Pcyc* —
24.51
24.52
Receive data hold time
(clock synchronization)
RTS delay time
CTS setup time
(clock synchronization)
CTS hold time
(clock synchronization)
t_RXH
t
RTSD
t
CTSS
t_CTSH
2 t_Pcyc* —
—
100
100 —
100 —
Note: * t_Pcyc indicates a peripheral clock (Pφ) cycle.
SCIFnCK
t_SCKW
t_SCKR
t_Scyc
t_SCKF
Figure 24.51 SCIFnCK Input Clock Timing
Rev.1.50 Aug. 30, 2006 Page 831 of 860
REJ09B0288-0150