SH7713 Datasheet, PDF (702/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.4.4 Accessing MII Registers
MII registers in the PHY-LSI are accessed via this LSI’s PHY interface register (PIR). Connection
is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u.
MII Management Frame Format: The format of an MII management frame is shown in figure
18.5. To access an MII register, a management frame is implemented by the program in
accordance with the procedures shown in MII Register Access Procedure.
Access Type
Item
PRE
ST
Number of bits 32
2
Read
1..1
01
Write
1..1
01
MII Management Frame
OP PHYAD REGAD TA
2
5
5
2
10
00001 RRRRR
Z0
01
00001 RRRRR
10
DATA
16
D..D
D..D
[Legend]
PRE: 32 consecutive 1s
ST:
Write of 01 indicating start of frame
OP: Write of code indicating access type
PHYAD: Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI address.
REGAD: Write of 0001 if the register address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI register address.
TA:
Time for switching data transmission source on MII interface
(a) Write: 10 written
(b) Read: Bus release (notation: Z0) performed
DATA: 16-bit data. Sequential write or read from MSB
(a) Write: 16-bit data write
(b) Read: 16-bit data read
IDLE: Wait time until next MII management format input
(a) Write: Independent bus release (notation: X) performed
(b) Read: Bus already released in TA; control unnecessary
Figure 18.5 MII Management Frame Format
IDLE
X
Rev.1.50 Aug. 30, 2006 Page 662 of 860
REJ09B0288-0150