SH7713 Datasheet, PDF (311/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
Table 9.2 Specifying Break Data Register
Bus Selection in
BBRB
BDB31 to BDB16
BDB15 to BDB0
L bus
LDB31 to LDB0
I bus
IDB31 to IDB0
X bus
XDB15 to XDB0
Don’t care
Y bus
Don’t care
YDB15 to YDB0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRB as the break data.
3. Set the data in bits 31 to 16 when including the value of the data bus as an L-bus
break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or
MOVS.W @As+Ix,Ds instruction.
9.2.7 Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data
specified by BDRB.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BDMB31 to All 0
BDMB 0
R/W Break Data Mask B
Specifies bits masked in the break data of channel B
specified by BDRB (BDB31 to BDB0).
0: Break data BDBn of channel B is included in the
break condition
1: Break data BDBn of channel B is masked and is not
included in the break condition
Note: n = 31 to 0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB.
3. Set the mask data in bits 31 to 16 when including the value of the data bus as an L-
bus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W
@As+,Ds, or MOVS.W @As+Ix,Ds instruction.
Rev.1.50 Aug. 30, 2006 Page 271 of 860
REJ09B0288-0150