SH7713 Datasheet, PDF (714/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
RR
0
R/W Receive Request
0: The receive function is disabled*
1: A receive descriptor is read, and the E-DMAC is
ready to receive
Note: * If the receive function is disabled during frame reception, write-back is not performed
successfully to the receive descriptor. Following pointers to read a receive descriptor
become abnormal and the E-DMAC can not operate successfully. In this case, to make
the E-DMAC reception enabled again, execute a software reset by the SWR bit in
EDMR. To make the E-DMAC reception disabled without executing a software reset,
specify the RE bit in ECMR. Next, after the E-DMAC has completed the reception and
write-back to the receive descriptor has been confirmed, disable the receive function of
this register.
19.2.4 Transmit Descriptor List Address Register (TDLAR)
TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bit in EDMR. This register must not be written to during transmission.
Modifications to this register should only be made while transmission is disabled by the TR bit
(= 0) in the E-DMAC transmit request register (EDTRR).
Initial
Bit
Bit Name Value R/W Description
31 to 0 TDLA31 to All 0
TDLA0
R/W Transmit Descriptor Start Address
The lower bits are set as follows according to the
specified descriptor length.
16-byte boundary: TDLA3 and TDLA0 = 0000
32-byte boundary: TDLA4 and TDLA0 = 00000
64-byte boundary: TDLA5 and TDLA0 = 000000
Rev.1.50 Aug. 30, 2006 Page 674 of 860
REJ09B0288-0150