SH7713 Datasheet, PDF (530/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
DREQ Pin Sampling Timing:
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
DMAC
CPU
1st acceptance
Non sensitive period
2nd acceptance
Acceptance start
Figure 13.12 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CPU
CPU
DMAC
1st acceptance
Non sensitive period
CPU
2nd acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
CPU
2nd acceptance
Acceptance
start
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Rev.1.50 Aug. 30, 2006 Page 490 of 860
REJ09B0288-0150