SH7713 Datasheet, PDF (681/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.2 EtherC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet
controller. The settings in this register are normally made in the initialization process following a
reset.
The operating mode setting must not be changed while the transmitting and receiving functions
are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Initial
Bit
Bit Name Value
31 to 13 
All 0
12
PRCEF 0
11

0
10

0
9
MPDE 0
8

0
7

0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W CRC Error Frame Reception Enable
0: A receive frame including a CRC error is received
as a frame with an error.
1: A receive frame including a CRC error is received
as a frame without an error.
When this bit is cleared to 0, the CRC error is
reflected in EESR of the E-DMAC and the status of
the receive descriptor. When this bit is set to 1, a
frame is received as a normal frame.
R
Reserved
R
These bits are always read as 0. The write value
should always be 0.
R/W Magic Packet Detection Enable
Enables or disables Magic Packet detection by
hardware to allow activation from the Ethernet.
0: Magic Packet detection is not enabled
1: Magic Packet detection is enabled
R
Reserved
R
These bits are always read as 0. The write value
should always be 0.
Rev.1.50 Aug. 30, 2006 Page 641 of 860
REJ09B0288-0150