SH7713 Datasheet, PDF (665/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
No.
Time Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set SCKE bit in SICTR to 1
3
Start SCK_SIO clock transmission
4
Set FSE bit in SICTR to 1
5
Set RXE bit in SICTR to 1
6
Store receive data from RXD_SIO
in SIRDR synchronously with SIOFSYNC
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and the upper limit value of FIFO
request
Set operation start for baud rate
generator
Set the start for frame
synchronous signal
Set to enable reception
Transmit serial clock
Transmit frame
synchronous signal
Submit reception request
according to the receive
FIFO threshold value
7
RDREQ=1? ^No
Yes
Reception
8
Read SIRDR
Read receive data
Receive
No
ended?
9
Yes
Clear RXE bit in SICTR to 0
End
Set to disable reception
End reception
Figure 17.10 Example of Reception Operation in Master Mode
Transmission in Slave Mode: Figure 17.11 shows an example of settings and operation for slave
mode transmission.
Rev.1.50 Aug. 30, 2006 Page 625 of 860
REJ09B0288-0150