SH7713 Datasheet, PDF (740/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
27
TFE
0
R/W Transmit Frame Error Occurrence
Indicates that an error occurred in the transmit frame.
The errors occurred in TFS8 (bit 8), or TFS3 to TFS0
(bits 3 to 0).
26 to 0 TFS26 to All 0
TFS0
R/W Transmit Frame Status
Indicate the status of the corresponding frame. A bit
below, when set to 1, indicates the occurrence of the
corresponding event. If the events of TFS8, or TFS3
to TFS0 occur, frames are incompletely transmitted.
TFS26 to TFS9: Reserved (The write value should
always be 0.)
TFS8: Transmit abort detected
Note: This bit is set when any bit of TFS3 to TFS0 is
set.
TFS7 to TFS4: Reserved (The write value should
always be 0)
TFS3: Failure to detect the carrier at the start of
transmission (corresponding to the CND bit in
EESR)
TFS2: Loss of the carrier during transmission
(corresponding to the DLC bit in EESR)
TFS1: Late (delayed) collision (corresponding to the
CD bit in EESR)
TFS0: Transmit retry over (corresponding to the TRO
bit in EESR)
Rev.1.50 Aug. 30, 2006 Page 700 of 860
REJ09B0288-0150