SH7713 Datasheet, PDF (372/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
5. Byte-selection SRAM interface
• Can connect directly to a byte-selection SRAM.
6. PCMCIA direct interface
• Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver 4.2
(PCMCIA2.1 Rev 2.1).
• Controls the insertion of the wait state using software.
• Supports the bus sizing function of the I/O bus width (only in little endian mode).
7. Burst ROM (clock synchronous) interface
• Can connect directly to a burst ROM of the clock synchronous type.
8. Bus arbitration
• Shares all of the resources with other CPU and outputs the bus enable after receiving the bus
request from external devices.
9. Refresh function
• Supports the auto-refresh and self-refresh functions.
• Specifies the refresh interval using the refresh counter and clock selection.
• Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
10. Interval timer using refresh counter
• Generates an interrupt request by a compare match.
The block diagram of the BSC is shown in figure 12.1.
Rev.1.50 Aug. 30, 2006 Page 332 of 860
REJ09B0288-0150