SH7713 Datasheet, PDF (612/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
When using a modem function and the receive FIFO (SCFRDR) is at least the number of the RTS
output trigger, the RTS signal goes high.
Receive data
RxD
Start
bit
0 D0 D1
Parity Stop
bit bit
D6 D7 0/1
RTS
RTS goes high when receive data is RTS goes low when receive data is
at least number of RTS output trigger less than number of RTS output trigger
Figure 16.10 RTS Control Operation
16.4.3 Serial Operation in Clock Synchronous Mode
In clock synchronous mode, the SCIF transmits and receives data synchronizing with clock pulses.
This mode is suitable for high-speed serial communication. In the SCIF, the transmitter and
receiver are independent. Therefore, by sharing the same clock, full-duplex communication can be
performed. Figure 16.11 shows the general format of clock synchronous serial communication.
*
Serial clock
One unit of transfer data (character or frame)
*
LSB
Serial data Don’t care Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
Bit 7 Don’t care
Note: * High except in continuous transmission/reception
Figure 16.11 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, data on the communication line is output from one
fall of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the MSB.
Rev.1.50 Aug. 30, 2006 Page 572 of 860
REJ09B0288-0150