SH7713 Datasheet, PDF (621/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initialization
Start transmission and reception
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data in SCFTDR and
read TDFE flag in SCFSR
Read ORER flag in SCLSR
ORER = 1?
No
Yes
Error handling
Read RDF flag in SCFSR
No
RDF = 1?
Yes
Read receive data in SCFRDR and
clear RDF flag in SCFSR to 0
1. SCIF initialization: See figure 16.3, Sample
SCIF Initialization Flowchart.
2. SCIF status check and receive data write:
Read SCFSR, check that the TDFE flag is
set to 1, then write transmit data in SCFTDR
and clear the TDFE flag to 0. Notification that
the TDFE flag has changed from 0 to 1 can
also be given by the TXI.
3. Receive error handling: If a receive error occurs,
read the ORER flag in SCLSR, then after
executing the necessary error handling, clear
the ORER flag to 0. Serial reception cannot be
continued while the ORER flag is set to 1.
4. SCIF status check and receive data read:
Read SCFSR, check that the RDF flag is set
to 1, then read receive data from SCFRDR
and clear the RDF flag to 0. Notification that
the RDF flag has changed from 0 to 1 can also
be given by the RXI.
5. Serial transmission/reception continuation
procedure: To continue serial reception, before
the MSB of the current frame is received, read
the RDF flag and SCFRDR and clear the RDF
flag to 0. Also, check that the TDFE flag is set
to 1 and data can be written before transmitting
the MSB of the current frame. Futhermore, write
data in SCFTDR and clear the TDFE flag to 0.
Note: When switching from transmission or reception
to simultaneous transmission and reception,
clear the TE and RE bits to 0, then set the both
bits to 1 simultaneously.
No
All data received?
Yes
Clear TE and RE bits in SCSCR to 0
End
Figure 16.18 Sample Serial Data Transmission/Reception Flowchart
Rev.1.50 Aug. 30, 2006 Page 581 of 860
REJ09B0288-0150