SH7713 Datasheet, PDF (361/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 11 On-Chip Oscillation Circuits
Initial
Bit
Bit Name Value R/W
Description
9
STC1
0
R/W
Frequency Multiplication Ratio of PLL Circuit 1
8
STC0
0
R/W
00: × 1 time
01: × 2 times
10: × 3 times
11: Reserved (setting prohibited)
7

0
R
Reserved
6

0
R
These bits are always read as 0. The write value
should always be 0.
5
IFC1
0
R/W
Internal Clock Frequency Division Ratio
4
IFC0
0
R/W
These bits specify the frequency division ratio of the
internal clock (Iφ) with respect to the output frequency
of PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: Reserved (setting prohibited)
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
PFC2
0
R/W
Peripheral Clock Frequency Division Ratio
1
PFC1
1
R/W
These bits specify the division ratio of the peripheral
0
PFC0
1
R/W
clock (Pφ) frequency with respect to the output
frequency of PLL circuit 1.
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
Other than above: Reserved (setting prohibited)
Rev.1.50 Aug. 30, 2006 Page 321 of 860
REJ09B0288-0150