SH7713 Datasheet, PDF (596/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Invalidates the transmit data in the transmit FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of
a power-on reset or manual reset.
1
RFRST
0
R/W Receive FIFO Data Register Reset
Invalidates the receive data in the receive FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of
a power-on reset or manual reset.
0
LOOP
0
R/W Loopback Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD), and RTS pin and CTS pin,
enabling loopback testing.
0: Loopback test disabled
1: Loopback test enabled
16.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and
SCFRDR.
Bits 12 to 8 show the number of transmit data bytes in SCFTDR, and bits 4 to 0 show the number
of receive data bytes in SCFRDR.
SCFDR can be read by the CPU at all times.
SCFDR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby
mode or in the module standby state, and retains its contents.
Rev.1.50 Aug. 30, 2006 Page 556 of 860
REJ09B0288-0150