SH7713 Datasheet, PDF (558/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 Realtime Clock (RTC)
Bit
7
6
5, 4
3 to 0
Bit Name
ENB
Initial Value R/W
0
R/W

0
R


R/W


R/W
Description
Date Alarm Enable
Specifies whether comparison of RDAYCNT and
RDAYAR is performed as an alarm condition.
0: Not compared
1: Compared
Reserved
This bit is always read as 0. The write value
should always be 0.
Setting value for 10-unit of date alarm in the
BCD-code.
The range can be set from 0 to 3 (decimal).
Setting value for 1-unit of date alarm in the BCD-
code.
The range can be set from 0 to 9 (decimal).
15.3.14 Month Alarm Register (RMONAR)
RMONAR is an alarm register corresponding to the month counter RMONCNT. When the ENB
bit is set to 1, a comparison with the RMONCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/ and RMONAR, the counter and alarm register
comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if
each of those coincide, an RTC alarm interrupt is generated.
The range of month alarm which can be set is 1 to 12 (decimal). Errant operation will result if any
other value is set.
RMONAR is an 8-bit readable/writable register. The ENB bit in RMONAR is initialized by a
power-on reset. The remaining RMONAR fields are not initialized by a power-on reset or manual
reset, or in standby mode.
Rev.1.50 Aug. 30, 2006 Page 518 of 860
REJ09B0288-0150