SH7713 Datasheet, PDF (735/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.3.1 Descriptors and Descriptor List
Two types of descriptors are available: transmit descriptors and receive descriptors. The E-DMAC
automatically starts reading a transmit/receive descriptor when the TR bit in EDTRR is set to 1 or
the RR bit in EDRRR is set to 1. In a transmit/receive descriptor, the user stores information about
DMA transfer of transmit/receive data. After completion of Ethernet frame transmission/reception,
the E-DMAC disables the descriptor valid/invalid bit and reflects the result of
transmission/reception in the status bits.
Descriptors are placed in a readable/writable memory space. The address of the start descriptor
(descriptor to be read first by the E-DMAC) is set in TDLAR/RDLAR. When multiple descriptors
are prepared as a descriptor row (descriptor list), the descriptors are placed in continuous
(memory) addresses according to the descriptor length set in the DL0 and DL1 bits in EDMR.
The E-DMAC consists of one system. The DMAC for transmission and the DMAC for reception
operate independently of each other. For normal E-DMAC operation, place descriptors for
transmission and reception in those address spaces that do not overlap.
(1) Transmit Descriptor
Figure 19.2 shows the configuration of a transmit descriptor and the relationship with a transmit
buffer.
The data of a transmit descriptor consists of TD0, TD1, TD2, and padding data in groups of 32
bits from top to end. The length of padding data is determined according to the descriptor length
specified by the DL0 and DL1 bits in EDMR. In the figure, TBA (bits 31 to 0 in TD2) indicates
the start address of a transmit buffer, and TDL (bits 31 to 16 in TD1) indicates the valid data
length of the transmit buffer.
TD0 indicates whether the transmit descriptor is valid or invalid as well as information about the
descriptor configuration and status. TD1 indicates the length of data in a transmit buffer to be
transferred according to the specification of the descriptor. TD2 indicates the start address of a
transmit buffer that holds data to be transferred.
Depending on the descriptor specification, one transmit descriptor can specify all transmit data of
one frame (single-frame/single-buffer) or multiple descriptors can specify the transmit data of one
frame (single-frame/multi-buffer). As an example of single-frame/multi-buffer operation, the data
portion that is used in a fixed manner in each Ethernet frame transmission can be referenced by
multiple descriptors. For example, multiple descriptors can share the destination address and
transmit source address in an Ethernet frame, and the remaining data can be stored in each
separate buffer.
Rev.1.50 Aug. 30, 2006 Page 695 of 860
REJ09B0288-0150