SH7713 Datasheet, PDF (307/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
9.2.2 Break Address Mask Register A (BAMRA)
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address
specified by BARA.
Bit
31 to 0
Bit Name
BAMA31 to
BAMA 0
Initial
Value R/W
All 0 R/W
Description
Break Address Mask A
Specify bits masked in the channel A break address
bits specified by BARA (BAA31–BAA0).
0: Break address bit BAAn of channel A is included in
the break condition
1: Break address bit BAAn of channel A is masked and
is not included in the break condition
Note: n = 31 to 0
9.2.3 Break Bus Cycle Register A (BBRA)
BBRA is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2)
instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of
channel A.
Bit
Bit Name
15 to 8 
7
CDA1
6
CDA0
Initial
Value R/W
All 0 R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
L Bus Cycle/I Bus Cycle Select A
Select the L bus cycle or I bus cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Rev.1.50 Aug. 30, 2006 Page 267 of 860
REJ09B0288-0150