SH7713 Datasheet, PDF (728/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.11 FIFO Depth Register (FDR)
FDR is a 32-bit readable/writable register that specifies the size of the transmit and receive FIFOs.
Initial
Bit
Bit Name Value R/W Description
31 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8 TFD2 to All 1
TFD0
R/W Transmit FIFO Size
Specifies 256 bytes to 2 kbytes in 256-byte units as
the size of the transmit FIFO. The setting must not be
changed after transmission/reception has started.
7 to 3 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 to 0 RFD2 to All 1
RFD0
R/W Receive FIFO Size
Specifies 256 bytes to 2 kbytes in 256-byte units as
the size of the receive FIFO. The setting must not be
changed after transmission/reception has started.
Rev.1.50 Aug. 30, 2006 Page 688 of 860
REJ09B0288-0150