SH7670 Datasheet, PDF (996/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Asynchronous Mode)
Figures 22.7 and 22.8 show sample flowcharts for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
[1] Receive error handling and
break detection:
Read ER, DR, BRK flags in
SCFSR and ORER
[1]
flag in SCLSR
ER, DR, BRK or ORER = 1?
Yes
No
Error handling
Read the DR, ER, and BRK
flags in SCFSR, and the
ORER flag in SCLSR, to
identify any error, perform the
appropriate error handling,
then clear the DR, ER, BRK,
and ORER flags to 0. In the
case of a framing error, a
break can also be detected by
reading the value of the RxD
pin.
Read RDF flag in SCFSR
[2]
[2] SCIF status check and receive
data read:
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
Read SCFSR and check that
RDF flag = 1, then read the
receive data in SCFRDR, read
1 from the RDF flag, and then
clear the RDF flag to 0. The
transition of the RDF flag from
0 to 1 can also be identified by
a receive FIFO data full
interrupt (RXI).
No
All data received?
[3]
[3] Serial reception continuation
procedure:
Yes
Clear RE bit in SCSCR to 0
End of reception
To continue serial reception,
read at least the receive
trigger set number of receive
data bytes from SCFRDR,
read 1 from the RDF flag, then
clear the RDF flag to 0. The
number of receive data bytes
in SCFRDR can be
ascertained by reading from
SCRFDR.
Figure 22.7 Sample Flowchart for Receiving Serial Data
Rev. 1.00 Nov. 14, 2007 Page 970 of 1262
REJ09B0437-0100