SH7670 Datasheet, PDF (231/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
7.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

 DEEP  RFSH RMODEPDOWN BACTV 

 A3ROW[1:0]

A3COL[1:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R R/W R/W R/W R/W R
R
R R/W R/W R R/W R/W
Bit
Bit Name
31 to 14 
13
DEEP
12

11
RFSH
Initial
Value
All 0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RFSH or
RMODE bit is set to 1 while this bit is set to 1, the deep
power-down entry command is issued and the low-
power SDRAM enters the deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
Rev. 1.00 Nov. 14, 2007 Page 205 of 1262
REJ09B0437-0100