SH7670 Datasheet, PDF (221/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
Bit
19 to 13
Bit Name

Initial
Value
All 0
12, 11 SW[1:0] 00
10 to 7 WR[3:0] 1010
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Delay Cycles from Address, CS6 Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address, CS6
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
R/W Number of Access Wait Cycles
Specify the number of cycles that are necessary for
read/write access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Rev. 1.00 Nov. 14, 2007 Page 195 of 1262
REJ09B0437-0100