SH7670 Datasheet, PDF (914/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.5 HIF Internal Interrupt Control Register (HIFIICR)
HIFIICR is a 32-bit register used to issue interrupts from an external device connected to the HIF
to the on-chip CPU. Access to HIFIICR by an external device should be performed with HIFIICR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0







 IIC6 IIC5 IIC4 IIC3 IIC2 IIC1 IIC0 IIR
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit Bit Name Value R/W Description
31 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
IIC6
0
R/W Internal Interrupt Source
6
IIC5
0
5
IIC4
0
4
IIC3
0
3
IIC2
0
2
IIC1
0
R/W These bits specify the source for interrupts generated by
R/W ^{the IIR bit. These bits can be written to from both an}
external device and the on-chip CPU. By using these bits,
R/W _{fast execution of interrupt exception handling is possible.}
R/W ^{These bits are completely under software control, and}
R/W ^{their values have no effect on the operation of this LSI.}
1
IIC0
0
R/W
0
IIR
0
R/W Internal Interrupt Request
While this bit is 1, an interrupt request (HIFI) is issued to
the on-chip CPU.
Rev. 1.00 Nov. 14, 2007 Page 888 of 1262
REJ09B0437-0100