SH7670 Datasheet, PDF (643/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 16 Serial Sound Interface (SSI)
16.4.5 Receive Operation
Like transmission, reception can be controlled either by DMA or interrupt.
Figures 16.22 and 16.23 show the flow of operation.
When disabling the SSI module, the SSI clock* must be kept supplied until the IIRQ bit is in idle
state.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Input clock from the AUDIO_CLK pin when SCKD = 1.
Rev. 1.00 Nov. 14, 2007 Page 617 of 1262
REJ09B0437-0100