SH7670 Datasheet, PDF (769/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Bit
Bit Name
13
CSCLR
Section 17 USB 2.0 Host/Function Module (USB)
Initial
Value
0
R/W
R/W*¹
Description
C-SPLIT Status Clear Bit
Setting this bit to 1 allows this module to clear the
CSSTS bit of the pertinent pipe to 0.
0: Writing invalid
1: Clears the CSSTS bit to 0.
For the transfer using the split transaction, to restart
the next transfer with the S-SPLIT forcibly, set this bit
to 1 through software. However, for the normal split
transaction, this module automatically clears the
CSSTS bit to 0 upon completion of the C-SPLIT;
therefore, clearing the CSSTS bit through software is
not necessary.
Controlling the CSSTS bit through this bit must be
done while UACT is 0 thus communication is halted
or while no transfer is being performed with bus
disconnection detected.
Setting this bit to 1 while CSSTS is 0 has no effect.
When the function controller function is selected, be
sure to write 0 to this bit.
Rev. 1.00 Nov. 14, 2007 Page 743 of 1262
REJ09B0437-0100