SH7670 Datasheet, PDF (525/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.2.1 Channel [i] Processing Control Register (C[i]C) (i = 0, 1)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16














 C[i]C_R
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit: _{15 14 13 12 11 10}
9
8
7
6
5
4
3
2
1
0



C[i]C_
DWF


C[i]C_

VLD


C[i]C_

EIE


 C[i]C_E
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: _R
R
R
R
R
R
R R/W R
R
R R/W R
R
R R/W
Bit
Bit Name
31 to 17 —
16
C[i]C_R
15 to 13 —
12
C[i]C_DWF
11 to 9 —
Initial
Value R/W
All 0 R
0
R/W
All 0 R
0
R
All 0 R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reset
Writing 1 to this bit when the channel [i] processor is
halted causes the channel [i] calculation sequence
to be reset. This bit is automatically and immediately
set to 0. Setting both this bit and the C[i]C_E bit to 1
causes channel [i] processing to be newly started.
Reserved
These bits are always read as 0. The write value
should always be 0.
WAIT State Flag after Descriptor Processing End
0: Non-WAIT state
1: WAIT state
There are two methods for understanding the
processing state of the DMAC channel [i] descriptor.
In one, when the DMAC channel [i] descriptor is set,
C[i]DWE is set to 1 and then C[i]DIE is set to 1 to
accept the "1 descriptor processing end" interrupt
request. In the other, the processing state is
observed till this bit is set to 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 499 of 1262
REJ09B0437-0100