SH7670 Datasheet, PDF (703/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
17.3.16 Interrupt Status Register 0 (INTSTS0)
INTSTS0 is a register that indicates the status of the various interrupts detected.
This register is initialized by a power-on reset. By a USB bus reset, the DVSQ2 to DVSQ0 bits are
initialized.
Bit: 15 14 13 12 11 10 9
8
7
VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS
Initial value: 0
0
0
0
0
0
0
0
*³
R/W: R/W*⁷ R/W*⁷ R/W*⁷ R/W*⁷ R/W*⁷ R
R
R
R
6
5
4
DVSQ[2:0]
*²
*²
*²
R
R
R
3
VALID
0
R/W*⁷
2
1
0
CTSQ[2:0]
0
0
0
RRR
Initial
Bit
Bit Name
Value R/W Description
15
VBINT
0
R/W*⁷ VBUS Interrupt Status*⁴*⁵
0: VBUS interrupts not generated
1: VBUS interrupts generated
This module sets this bit to 1 on detecting a level
change (high to low or low to high) in the VBUS pin
input value. This module sets the VBSTS bit to
indicate the VBUS pin input value. When the VBUS
interrupt is generated, use software to repeat reading
the VBSTS bit until the same value is read three or
more times, and eliminate chattering.
14
RESM
0
R/W*⁷ Resume Interrupt Status*⁴*⁵*⁶
0: Resume interrupts not generated
1: Resume interrupts generated
When the function controller function is selected, this
module sets this bit to 1 on detecting the falling edge
of the signal on the DP pin in the suspended state
(DVSQ = 1XX).
When the host controller function is selected, the
read value is invalid.
Rev. 1.00 Nov. 14, 2007 Page 677 of 1262
REJ09B0437-0100