SH7670 Datasheet, PDF (596/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3.14 STIF Debugging Status Register (STDBGR)
STDBGR is a 32-bit register that indicates the first four bytes of an input or output packet.
STDBGR is provided for debugging. The write value should always be 0.
Initial
Bit
Bit Name Value
31 to 0 STMON31 All 0
to STMON0
R/W Description
R The 4-byte timestamp of a packet that is input or output in
TS mode is stored.
15.4 Examples of Clock Connection to Another Device
Examples of clock connection to another device are illustrated below.
15.4.1 A Basic Example
Another device
CLKOUT (output)
CLKIN (input)
SYC (input/output)
VLD (input/output)
D[7:0] (input/output)
This LSI
ST0_CLKIN (input)
ST_CLKOUT (output)
STn_SYC (input/output)
STn_VLD (input/output)
STn_D[7:0] (input/output)
(n = 0, 1)
• When this LSI receives a stream, it is received in synchronization with STn_CLKIN.
• When this LSI sends a stream, it is sent in synchronization with ST_CLKOUT.
15.4.2 An Example of Clock Connection When Another Device Has No Clock Input
Another device
CLKOUT (output)
SYC (input/output)
VLD (input/output)
D[7:0] (input/output)
This LSI
open
ST0_CLKIN (input)
ST_CLKOUT (output)
STn_SYC (input/output)
STn_VLD (input/output)
STn_D[7:0] (input/output)
(n = 0, 1)
• When this LSI receives a stream, it is received in synchronization with STn_CLKIN.
• When this LSI sends a stream, it is sent in synchronization with STn_CLKIN.
Rev. 1.00 Nov. 14, 2007 Page 570 of 1262
REJ09B0437-0100