SH7670 Datasheet, PDF (1079/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 24 I/O Ports
24.5.2 Port E Data Register L (PEDRL)
PEDRL is a 16-bit readable/writable register that stores port E data. Bits PE11DR to PE0DR
correspond to pins PE11 to PE00, respectively (description of the other functions are omitted).
If a pin is set to the general output function, the pin will output the value written to the
corresponding bit in PEDRL, and the register value is read from PEDRL regardless of the state of
the pin.
If a pin is set to the general input function, the pin state, not the register value, will be returned if
PEDRL is read. Also, if a value is written to PEDRL, although the value will actually be written, it
will have no influence on the state of the pin.Table 24.5 summarizes the PEDRL read/write
operations.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
PE11 PE10 PE9 PE8 PE7
DR
DR DR DR DR
PE6 PE5
DR
DR
PE4 PE3 PE2 PE1 PE0
DR DR DR DR
DR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to
12
Bit Name
—
11
PE11DR
10
PE10DR
9
PE9DR
8
PE8DR
7
PE7DR
6
PE6DR
5
PE5DR
4
PE4DR
3
PE3DR
2
PE2DR
1
PE1DR
0
PE0DR
Initial
Value R/W
All 0 R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
See table 24.5.
Rev. 1.00 Nov. 14, 2007 Page 1053 of 1262
REJ09B0437-0100