SH7670 Datasheet, PDF (432/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
12.3.4 PHY Interface Register (PIR)
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY registers via
the MII.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
MDI MDO MMD MDC
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0 Undefined 0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W
Bit Bit Name
31 to 4 
3
MDI
2
MDO
1
MMD
0
MDC
Initial
Value
R/W Description
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
Undefined R MII Management Data-In
Indicates the level of the MDIO pin.
0
R/W MII Management Data-Out
Outputs the value set to this bit from the MDIO pin,
when the MMD bit is 1.
0
R/W MII Management Mode
Specifies the data read/write direction with respect to
the MII.
0: Read direction is indicated
1: Write direction is indicated
0
R/W MII Management Data Clock
Outputs the value set to this bit from the MDC pin and
supplies the MII with the management data clock. For
the method of accessing the MII registers, see section
12.4.4, Accessing MII Registers.
Rev. 1.00 Nov. 14, 2007 Page 406 of 1262
REJ09B0437-0100