SH7670 Datasheet, PDF (21/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 18 SD Host Interface (SDHI)................................................................831
Section 19 I²C Bus Interface 3 (IIC3) ................................................................833
19.1 Features............................................................................................................................. 833
19.2 Input/Output Pins.............................................................................................................. 835
19.3 Register Descriptions........................................................................................................ 836
19.3.1 I²C Bus Control Register 1 (ICCR1)................................................................. 836
19.3.2 I²C Bus Control Register 2 (ICCR2)................................................................. 839
19.3.3 I²C Bus Mode Register (ICMR)........................................................................ 841
19.3.4 I²C Bus Interrupt Enable Register (ICIER) ....................................................... 843
19.3.5 I²C Bus Status Register (ICSR)......................................................................... 845
19.3.6 Slave Address Register (SAR).......................................................................... 848
19.3.7 I²C Bus Transmit Data Register (ICDRT)......................................................... 848
19.3.8 I²C Bus Receive Data Register (ICDRR).......................................................... 849
19.3.9 I²C Bus Shift Register (ICDRS)........................................................................ 849
19.3.10 NF2CYC Register (NF2CYC) .......................................................................... 850
19.4 Operation .......................................................................................................................... 851
19.4.1 I²C Bus Format.................................................................................................. 851
19.4.2 Master Transmit Operation ............................................................................... 852
19.4.3 Master Receive Operation................................................................................. 854
19.4.4 Slave Transmit Operation ................................................................................. 856
19.4.5 Slave Receive Operation................................................................................... 859
19.4.6 Clocked Synchronous Serial Format................................................................. 860
19.4.7 Noise Filter ....................................................................................................... 864
19.4.8 Example of Use................................................................................................. 865
19.5 Interrupt Requests ............................................................................................................. 869
19.6 Bit Synchronous Circuit.................................................................................................... 870
19.7 Usage Notes ...................................................................................................................... 873
19.7.1 Notes on Working in Multi-master Mode......................................................... 873
19.7.2 Notes on Working in Master Receive Mode..................................................... 873
19.7.3 Notes on Setting ACKBT in Master Receive Mode ......................................... 873
19.7.4 Notes on the States of MST and TRN Bits when Arbitration Is Lost ............... 874
Section 20 Host Interface (HIF).........................................................................875
20.1 Features............................................................................................................................. 875
20.2 Input/Output Pins.............................................................................................................. 877
20.3 Parallel Access.................................................................................................................. 878
20.3.1 Operation .......................................................................................................... 878
20.3.2 Connection Method........................................................................................... 878
20.4 Register Descriptions........................................................................................................ 879
Rev. 1.00 Nov. 14, 2007 Page xxi of xxvi