SH7670 Datasheet, PDF (330/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
Bit
Bit Name
29
RLDSAR
28
RLDDAR
27 to 24 
23
DO
22
TL
Initial
Value
0
0
All 0
0
0
R/W Descriptions
R/W SAR Reload Function Enable or Disable
Sets whether to enable or disable the reload function
for SAR or DMATCR.
0: Disables the reload function for SAR or DMATCR.
1: Enables the reload function for SAR or DMATCR.
R/W DAR Reload Function Enable or Disable
Sets whether to enable or disable the reload function
for DAR or DMATCR.
0: Disables the reload function for DAR or DMATCR.
1: Enables the reload function for DAR or DMATCR.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR_0 and
CHCR_1. This bit is reserved in CHCR_2 to CHCR_7;
it is always read as 0 and the write value should always
be 0.
0: Detects DREQ by overrun 0.
1: Detects DREQ by overrun 1.
R/W Transfer End Level
Specifies the TEND signal output is high active or low
active. This bit is valid only in CHCR_0 and CHCR_1.
This bit is reserved in CHCR_2 to CHCR_7; it is always
read as 0 and the write value should always be 0.
0: Low-active output from TEND
1: High-active output from TEND
Rev. 1.00 Nov. 14, 2007 Page 304 of 1262
REJ09B0437-0100