SH7670 Datasheet, PDF (20/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

17.3.16 Interrupt Status Register 0 (INTSTS0) ............................................................. 677
17.3.17 Interrupt Status Register 1 (INTSTS1) ............................................................. 682
17.3.18 BRDY Interrupt Status Register (BRDYSTS).................................................. 688
17.3.19 NRDY Interrupt Status Register (NRDYSTS) ................................................. 689
17.3.20 BEMP Interrupt Status Register (BEMPSTS) .................................................. 691
17.3.21 Frame Number Register (FRMNUM)............................................................... 692
17.3.22 µFrame Number Register (UFRMNUM) ......................................................... 695
17.3.23 USB Address Register (USBADDR)................................................................ 696
17.3.24 USB Request Type Register (USBREQ) .......................................................... 697
17.3.25 USB Request Value Register (USBVAL) ........................................................ 699
17.3.26 USB Request Index Register (USBINDX) ....................................................... 700
17.3.27 USB Request Length Register (USBLENG) .................................................... 701
17.3.28 DCP Configuration Register (DCPCFG).......................................................... 702
17.3.29 DCP Maximum Packet Size Register (DCPMAXP) ........................................ 703
17.3.30 DCP Control Register (DCPCTR) .................................................................... 704
17.3.31 Pipe Window Select Register (PIPESEL)......................................................... 714
17.3.32 Pipe Configuration Register (PIPECFG) .......................................................... 716
17.3.33 Pipe Buffer Setting Register (PIPEBUF).......................................................... 723
17.3.34 Pipe Maximum Packet Size Register (PIPEMAXP)......................................... 726
17.3.35 Pipe Timing Control Register (PIPEPERI)....................................................... 728
17.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)........................................... 730
17.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)........... 750
17.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) ...................... 752
17.3.39 Device Address n Configuration Registers (DEVADDn) (n = 0 to A)............. 754
17.3.40 Bus Wait Register (D0FWAIT, D1FWAIT)..................................................... 757
17.4 Operation .......................................................................................................................... 758
17.4.1 System Control and Oscillation Control ........................................................... 758
17.4.2 Interrupt Functions............................................................................................ 761
17.4.3 Pipe Control ...................................................................................................... 784
17.4.4 FIFO Buffer Memory........................................................................................ 794
17.4.5 Control Transfers (DCP)................................................................................... 804
17.4.6 Bulk Transfers (PIPE1 to PIPE5) ..................................................................... 808
17.4.7 Interrupt Transfers (PIPE6 to PIPE9) ............................................................... 810
17.4.8 Isochronous Transfers (PIPE1 and PIPE2) ....................................................... 811
17.4.9 SOF Interpolation Function .............................................................................. 823
17.4.10 Pipe Schedule.................................................................................................... 824
17.5 Usage Notes ...................................................................................................................... 826
17.5.1 Power Supplies for the USB Module................................................................ 826
17.5.2 DTCH Interrupt ................................................................................................ 830
Rev. 1.00 Nov. 14, 2007 Page xx of xxvi